library verilog;
use verilog.vl_types.all;
entity PWM_TOP is
    port(
        i_sys_clk       : in     vl_logic;
        i_sys_rst       : in     vl_logic;
        i_compare_set_value: in     vl_logic_vector(6 downto 0);
        o_compare_result: out    vl_logic
    );
end PWM_TOP;
